16 #ifdef __MSP430_HAS_USCI_Ax__
21 bool USCI_A_UART_init(uint16_t baseAddress, USCI_A_UART_initParam *
param)
26 HWREG8(baseAddress + OFS_UCAxCTL1) |= UCSWRST;
29 HWREG8(baseAddress + OFS_UCAxCTL1) &= ~UCSSEL_3;
30 HWREG8(baseAddress + OFS_UCAxCTL1) |=
param->selectClockSource;
33 HWREG8(baseAddress + OFS_UCAxCTL0) &= ~UCMSB;
34 HWREG8(baseAddress + OFS_UCAxCTL0) |=
param->msborLsbFirst;
38 HWREG8(baseAddress + OFS_UCAxCTL0) &= ~UCSPB;
39 HWREG8(baseAddress + OFS_UCAxCTL0) |=
param->numberofStopBits;
43 switch (
param->parity){
44 case USCI_A_UART_NO_PARITY:
46 HWREG8(baseAddress + OFS_UCAxCTL0) &= ~UCPEN;
48 case USCI_A_UART_ODD_PARITY:
50 HWREG8(baseAddress + OFS_UCAxCTL0) |= UCPEN;
51 HWREG8(baseAddress + OFS_UCAxCTL0) &= ~UCPAR;
53 case USCI_A_UART_EVEN_PARITY:
55 HWREG8(baseAddress + OFS_UCAxCTL0) |= UCPEN;
56 HWREG8(baseAddress + OFS_UCAxCTL0) |= UCPAR;
61 HWREG16(baseAddress + OFS_UCAxBRW ) =
param->clockPrescalar;
62 HWREG8(baseAddress + OFS_UCAxMCTL) = ((
param->firstModReg<<4) +
63 (
param->secondModReg <<1) +
64 param->overSampling );
67 HWREG8(baseAddress + OFS_UCAxCTL0) &= ~(UCSYNC +
73 HWREG8(baseAddress + OFS_UCAxCTL0) |=
param->uartMode ;
76 HWREG8(baseAddress + OFS_UCAxCTL1) &= ~(UCRXEIE + UCBRKIE + UCDORM +
81 void USCI_A_UART_transmitData ( uint16_t baseAddress,
86 if (!(
HWREG8(baseAddress + OFS_UCAxIE) & UCTXIE)){
88 while (!(
HWREG8(baseAddress + OFS_UCAxIFG) & UCTXIFG));
94 uint8_t USCI_A_UART_receiveData (uint16_t baseAddress)
97 if (!(
HWREG8(baseAddress + OFS_UCAxIE) & UCRXIE)){
99 while (!(
HWREG8(baseAddress + OFS_UCAxIFG) & UCRXIFG));
102 return (
HWREG8(baseAddress + OFS_UCAxRXBUF)) ;
105 void USCI_A_UART_enableInterrupt (uint16_t baseAddress,
111 locMask = (mask & (USCI_A_UART_RECEIVE_INTERRUPT
112 | USCI_A_UART_TRANSMIT_INTERRUPT));
113 HWREG8(baseAddress + OFS_UCAxIE) |= locMask;
115 locMask = (mask & (USCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT
116 | USCI_A_UART_BREAKCHAR_INTERRUPT));
117 HWREG8(baseAddress + OFS_UCAxCTL1) |= locMask;
120 void USCI_A_UART_disableInterrupt (uint16_t baseAddress,
126 if(locMask = (mask & (USCI_A_UART_RECEIVE_INTERRUPT
127 | USCI_A_UART_TRANSMIT_INTERRUPT))) {
128 HWREG8(baseAddress + OFS_UCAxIE) &= ~locMask;
131 if(locMask = (mask & (USCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT
132 | USCI_A_UART_BREAKCHAR_INTERRUPT))) {
133 HWREG8(baseAddress + OFS_UCAxCTL1) &= ~locMask;
137 uint8_t USCI_A_UART_getInterruptStatus (uint16_t baseAddress,
140 return (
HWREG8(baseAddress + OFS_UCAxIFG) & mask );
143 void USCI_A_UART_clearInterrupt (uint16_t baseAddress, uint8_t mask)
146 HWREG8(baseAddress + OFS_UCAxIFG) &= ~(mask);
149 void USCI_A_UART_enable (uint16_t baseAddress)
152 HWREG8(baseAddress + OFS_UCAxCTL1) &= ~(UCSWRST);
155 void USCI_A_UART_disable (uint16_t baseAddress)
158 HWREG8(baseAddress + OFS_UCAxCTL1) |= UCSWRST;
161 uint8_t USCI_A_UART_queryStatusFlags (uint16_t baseAddress,
164 return (
HWREG8(baseAddress + OFS_UCAxSTAT) & mask );
167 void USCI_A_UART_setDormant (uint16_t baseAddress)
169 HWREG8(baseAddress + OFS_UCAxCTL1) |= UCDORM;
172 void USCI_A_UART_resetDormant (uint16_t baseAddress)
174 HWREG8(baseAddress + OFS_UCAxCTL1) &= ~UCDORM;
177 void USCI_A_UART_transmitAddress (uint16_t baseAddress,
181 HWREG8(baseAddress + OFS_UCAxCTL1) |= UCTXADDR;
187 void USCI_A_UART_transmitBreak (uint16_t baseAddress)
190 HWREG8(baseAddress + OFS_UCAxCTL1) |= UCTXBRK;
193 if (USCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE ==
194 (
HWREG8(baseAddress + OFS_UCAxCTL0) &
195 USCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE)){
196 HWREG8(baseAddress + OFS_UCAxTXBUF) = USCI_A_UART_AUTOMATICBAUDRATE_SYNC;
198 HWREG8(baseAddress + OFS_UCAxTXBUF) = DEFAULT_SYNC;
202 if (!(
HWREG8(baseAddress + OFS_UCAxIE) & UCTXIE)){
204 while (!(
HWREG8(baseAddress + OFS_UCAxIFG) & UCTXIFG));
208 uint32_t USCI_A_UART_getReceiveBufferAddressForDMA (uint16_t baseAddress)
210 return ( baseAddress + OFS_UCAxRXBUF );
213 uint32_t USCI_A_UART_getTransmitBufferAddressForDMA (uint16_t baseAddress)
215 return ( baseAddress + OFS_UCAxTXBUF );
MPU_initThreeSegmentsParam param